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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-27243-1E
ASSP For Power Supply Applications
(Switching FET Integrated DC/DC Converter)
1ch PFM/PWM Synchronous Rectification Step-down Regulator
MB39C001
s DESCRIPTION
The MB39C001 is a synchronous rectification type of single-channel, step-down DC/DC converter IC using current mode control. The MB39C001 integrates switching FETs, an oscillator, error amplifier, voltage detector, and a reference voltage generator in a 18-pin BCC package. The required external components are only a coil and decoupling capacitors. The MB39C001 is small in size, and can achieve a DC/DC converter highly effective in the full load range, and it is the best for internal power supplies for portable devices such as cellular phones, PDAs and DSC.
s FEATURES
* * * * * * * High efficiency Quiescent current Output current (DC/DC) Input voltage range Oscillation frequency No flyback diode needed Low dropout operation : : : : : 96% Max 20 A (in PFM mode) 600 mA Max 2.5 V to 5.5 V 1.0 MHz (in PWM mode)
: 100% on-duty support
(Continued)
s PACKAGE
18-pin plastic BCC
(LCC-18P-M05)
www..com
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MB39C001
(Continued) * High-precision reference voltage generator integrated : 1.25 V 2% (with no load) * Output voltage select function integrated : Capable of selecting internal setting (3 bits) or external setting * Built-in switching FETs : PMOS 0.43 (Typ) , NMOS 0.32 (Typ) * Current mode control providing quick transition response to inputs/loads * Built-in temperature protection function * Low consumption current at shutdown mode : 1 A or less * Built-in undervoltage lockout protection circuit (UVLO) : Circuit actuation voltage of 2.3 V (Typ) * Small package : BCC-18P
2
MB39C001
s PIN ASSIGNMENT
(TOP VIEW)
DVDD1 VSET1 VSET2 VSET3
DVDD2
15
14
13
12
11
10
AVDD
VSEL
16
9
CNT
DGND1
17
MB39C001
8
AGND
DGND2
18
7
VREFIN
6 1 2 3 4 5
POWER GOOD
LX1
LX2
VRSEL
OUT
VREF
LCC-18P-M05
s PIN DESCRIPTION
Pin No. 1, 2 3 4 5 6 7 8 9 10 11 12 13 14, 15 16 17, 18 Symbol LX1, LX2 VRSEL OUT VREF POWER GOOD VREFIN AGND CNT AVDD VSET3 VSET2 VSET1 DVDD1, DVDD2 VSEL DGND1, DGND2 I/O O I I O O I I I I I I Drive block power-supply terminal. Output voltage switch terminal. (Refer (2) "Setting output voltages" in s APPLICATION NOTES.) Drive block ground terminal. 3 Output voltage setting terminal. (Refer (2) "Setting output voltages" in s APPLICATION NOTES) Description Inductor connection output terminals. Connect mutually and use the LX1 and LX2 terminal. They enter the high impedance state at shutdown. Reference voltage switch terminal. (Refer (2) "Setting output voltages" in s APPLICATION NOTES) Output voltage feedback terminal. Reference voltage (1.25 V) output terminal. POWERGOOD circuit output terminal. An N-ch MOS open-drain circuit is connected. Error amplifier (ErrorAmp) noninverting input terminal. Control block ground terminal. Control input terminal (L : Shutdown, H : Normal operation ) . Control block power-supply terminal.
MB39C001
s I/O TERMINAL EQUIVALENT CIRCUIT DIAGRAM
DVDD1 DVDD2
AVDD LX1 LX2 VREF
DGND1 DGND2
AGND
AVDD POWER GOOD VRSEL, VSET1, VSET2, VSET3, VSEL AGND AGND
AVDD
VREFIN AGND
OUT
AVDD CNT AGND
* : ESD protection element 4
MB39C001
s BLOCK DIAGRAM
VIN AVDD DVDD2 DVDD1 10 15 14 CNT OUT 9 4
To each block
- + ERR Amplifier Iout Comparator
R 6 POWER GOOD DET
VSEL VSET1 VSET2 VSET3
16 13 12 11
PFM/PWM Logic Control SELECT 1 2
LX1 L LX2
VOUT
C
VREF
5 1.25 V Ref VREFIN 7 3 VRSEL AGND 8 18 17 DGND2 DGND1
5
MB39C001
s FUNCTIONS
About the Current Mode Conventional voltage mode control compares the voltage (Vc) obtained by applying negative feedback to the output voltage using the ErrAmp with the reference triangular waveform (Vtri) to control the on-duty cycle, thereby regulating the output voltage. Current mode control uses the oscillator (rectangular waveform generator) , and the voltage (VIDET) obtained by applying I-V conversion to the current which flows into SW FET, and uses them in place of the triangular waveform. Current-mode control compares the voltage (Vc) obtained by applying negative feedback to the output voltage using the ErrAmp with VIDET to control the on-duty cycle, thereby regulating the output voltage.
Voltage mode control model
VIN
Current mode control model
VIN
Oscillator
Vc - + VIDET Vc Vtri tON Vc - + S R Q SR-FF
Vtri
VIDET Vc tOFF
tOFF
tON
Note : The above models illustrate principles of operation; they are slightly different from actual operations of the IC.
Function of Each Block * PFM/PWM Logic Control Circuit This circuit controls the synchronous rectification of internal P-channel MOS FET and N-channel MOS FET at the frequency (1 MHz), set by the internal oscillator (rectangular waveform oscillator) during normal operation. Under light loads, the circuit performs intermittent (burst) operation. The precaution of the penetration current caused by synchronous rectification and the reverse current flowing during discontinuous operation are performed to this circuit. * Iout Comparator Circuit This circuit detects the current (ILX) flowing from the internal P-channel MOS FET to the external inductor. The circuit compares the output of ErrAmp with VIDET, obtained by applying I-V conversion to the ILX peak current (IPK), and approaches the PFM/PWM Logic Control circuit to turn off the internal P-channel MOS FET.
6
MB39C001
* ErrAmp phase compensation circuit This circuit compares reference voltages such as VREF with output voltages. The IC contains a phase compensation circuit and adjusted for the best operation of this IC, and it is eliminating the need for nominating a phase compensation circuit and adding an external component for phase compensation. * VREF circuit A high-accuracy reference voltage is generated by a BGR (band gap reference) circuit. The output voltage is 1.25 V (Typ). * SELECT circuit This circuit is used to select a pre-set output voltage. The voltage can be set by changing the division resistance value at the earlier stage of the ErrAmp. * DET circuit This circuit monitors the OUT terminal voltage. When that voltage reaches the output set voltage, the opendrain output at the POWER GOOD terminal is turned on. * Protection circuit An over temperature protection circuit is built in the IC as a protection circuit. The over temperature protection circuit turns off both of the N-channel and P-channel SW FETs when the junction temperature reaches 135C. Also, when the junction temperature falls to 110 C, the over temperature protection circuit operates normally. Although the IC has no overcurrent protection circuit as a dedicated circuit, it uses current mode control for voltage control, and thus the peak-current value is monitored and controlled at any time. (The maximum peakcurrent value is 1 A.)
7
MB39C001
s ABSOLUTE MAXIMUM RATINGS
Ratings Min -0.3 -0.3 -0.3 -0.3 -40 - 55 Max 7 VDD + 0.3 VDD + 0.3 VDD + 0.3 7 VDD + 0.3 1.3 540* + 85 + 125 V V A mV C C V V Unit
Parameter Power supply voltage
Symbol VIN
Condition AVDD, DVDD1, and DVDD2 terminals OUT terminal CNT, VSEL, VSET1, VSET2, VSET3, and VRSEL terminals VREFIN terminal LX1/LX2 terminal LX1/LX2 terminal Ta + 25 C
Input voltage
VI
POWER GOOD pull-up voltage LX voltage LX peak current Power dissipation Operating ambient temperature Storage temperature
VIPG VLX IPK PD Ta TSTG
* : The package is mounted on a 10x10-cm square, dual sided epoxy board. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Values Min 2.5 0.3 -- -- Typ 3.7 -- -- -- Max 5.5 0.7 600 1
Parameter Power supply voltage VREFIN voltage LX current POWERGOOD current
Symbol VIN VRIN ILX IPG
Condition AVDD, DVDD1, and DVDD2 terminals -- VIN - VOUT 0.7 V* --
Unit V V mA mA
* : The output possible current can be tends to decrease when the voltage difference between the power supply voltage (VIN) and DC/DC converter output voltage (VOUT) is small. This is because of an effect of slope compensation; it does not lead to the breakdown of the device. If it is the using condition which suppresses the output current, it is possible to use it also with "VIN-VOUT<0.7 V". WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
8
MB39C001
s ELECTRICAL CHARACTERISTICS
(Unless otherwise specified , VIN = 3.7 V, CNT = 3.7 V, VSET1 = VSET2 = 0 V, VSET3 = VSEL = 3.7 V, VRSEL = 0 V, Ta = +25C) Parameter Reference voltage Input current Output voltage Input stability Load stability OUT terminal Input impedance LX peak current Oscillation frequency Rise delay time SW PMOS-FET ON resistor SW NMOS-FET ON resistor SW FET leak current Output voltage select block Input threshold voltage Input current Over temperature protection (junction temperature)
Symbol Pin No.
Condition VREF = 0 mA Load current = -200 mA*
l 2
Values Min 1.21 1.764 Typ 1.25 -40 1.8 1.01 1 1.0 170 80 0.43 0.32 1.0 0 0.1 135* 110* 2.3 2.15 0.15 Max 1.29 1.836 40 20 1.2 240 1 1.5 1 1
Unit V nA V mV mV M A MHz kHz s A V A A C C V V V
VREF IREFIN VOUT Line Load ROUT IPK fosc fSHORT tPG RPMOS RNMOS ILEAK VTH
5 7
VREFIN = 0.6 V, VRSEL = 3.7 V -100 2.5 V < DVDD = AVDD < 5.5 V* Load current = 0 mA
4
-200 mA > Load current > -600 mA OUT = 2.0 V OUT = 90% OUT = 0 V LX1 + LX2 = -100 mA
DC/DC converter block
1, 2 6
0.8 100 0.3
1, 2
LX1 + LX2 = 100 mA
3,9,11, CNT, VSEL, VSET1, VSET2, 12,13,16 VSET3, VRSEL terminal 9 CNT terminal 3,11,12, VSEL, VSET1, VSET2, VSET3, 13,16 VRSEL terminal 4 4, 10, 14, 15
II TOTPH TOTPL VTHH VTHL VHYS
Protection circuit UVLO block threshold voltage UVLO hysteresis width * : Standard design value
(Continued)
9
MB39C001
(Continued) (Unless otherwise specified , VIN = 3.7 V, CNT = 3.7 V, VSET1 = VSET2 = 0 V, VSET3 = VSEL = 3.7 V, VRSEL = 0 V, Ta = +25C)
Parameter Threshold voltage
Symbol Pin No.
Condition *3
Values Min 86 84 Typ 90 88 2 20 300 Max 94 92 0.1 1 1 35 400
Unit % % % V A A A A
VTHHPG VTHLPG VHYSPG VOL IOH IVDD1 IVDD2 IVDD3 6 4, 6
POWER GOOD Hysteresis width circuit Output voltage block Output current
POWER GOOD = 25 A POWER GOOD = 5.5 V CNT = 0 V, All circuits = OFF*4
Power supply current at shutdown General Power supply current on standby Power supply current during operation * : Standard design value
10, 14, Load current = 0 mA 15 VOUT = 90% or OUT = 1.62 V*5
*1 : Refer (2) "Setting output voltages" in s APPLICATION NOTES.) *2 : The minimum VIN value is 2.5 V or "output voltage setting value + 0.4 V", either high one. *3 : Detection to the output voltage setting value by VSET1 to VSET3. Refer (2) "Setting output voltages" in s APPLICATION NOTES.) *4 : The sum of the currents flowing to the AVDD terminal, DVDD1 terminal, and DVDD2 terminal. *5 : Current consumption at a duty cycle of 100% (with the main SW FET full-on). The SW FET gate drive current is not included because of a full-on state (not performing SW operation). And, the load current is not similarly included.
10
MB39C001
s TYPICAL OPERATING CHARACTERISTICS
(The following characteristics are provided for setup reference purposes only; they are not guaranteed characteristics.)
Conversion efficiency vs. Load current
100 95
Conversion efficiency vs. Load current
100 95
Conversion efficiency (%) %
90 85 80 75 70 65 60 55 50 0.1 1 VIN = 2.7 V VIN = 3.7 V VIN = 4.5 V Ta = +25 C L = 3.3 H C = 10 F VOUT = 1.8 V 10 100 1000
Conversion efficiency (%) %
90 85 80 75 70 65 60 55 50 0.1 1 10 100 1000 VIN = 2.7 V VIN = 3.7 V VIN = 4.5 V Ta = +25 C L = 3.3 H C = 10 F VOUT = 2.5 V
Load current IOUT (mA)
Load current IOUT (mA)
Conversion efficiency vs. Load current
100 95 1.84
Output voltage vs. Load current
Conversion efficiency (%) %
85 80 75 70 65 60 55 50 0.1 1 10 Ta = +25 C L = 3.3 H C = 10 F VOUT = 3.3 V 100 1000 VIN = 3.7 V VIN = 4.5 V
Output voltage VOUT (V)
90
1.82
1.80
1.78
1.76
1.74 0 100 200 300
Ta = +25 C VIN = 3.7 V VOUT = 1.8 V 400 500 600
Load current IOUT (mA)
Load current IOUT (mA)
(Continued)
11
MB39C001
Output voltage vs. Power supply voltage
1.90 1.88
Reference voltage vs. Ambient temperature
1.30
Reference voltage VREF (V)
Output voltage VOUT (V)
1.86 1.84 1.82 1.80 1.78 1.76 1.74 1.72 1.70 2.0 3.0 4.0 5.0 6.0 Ta = +25 C VOUT = 1.8 V IOUT = 600 mA IOUT = 0 A
1.28
1.26
IOUT = 0 A
1.24
IOUT = 600 mA
1.22 VIN = 3.7 V VOUT = 1.8 V 1.20 -50 -25 0 25 50 75 100
Power supply voltage VIN (V)
Ambient temperature Ta ( C)
Oscillation frequency vs. Power supply voltage
1.2
Oscillation frequency vs. Ambient temperature
1.2
Oscillation frequency fosc (MHz)
1.1
Oscillation frequency fosc (MHz)
1.1
1.0
1.0
0.9 Ta = +25 C VOUT = 1.8 V IOUT = 600 mA 0.8 2 3 4 5 6
0.9 VIN = 3.7 V IOUT = 600 mA 0.8 -50
Power supply voltage VIN (V)
Ambient temperature Ta ( C)
-25
0
25
50
75
100
(Continued)
12
MB39C001
Power supply current vs. Power supply voltage
50 45 50 45
Power supply current vs. Ambient temperature
Power supply current IIN (A)
40 35 30 25 20 15 10 5 0 2 3 4 5 6 Ta = +25 C VIN = 3.7 V VOUT = 1.8 V IOUT = 0 A
Power supply current IIN (A)
40 35 30 25 20 15 10 5 0 -50 -25 0 25 50 VIN = 3.7 V VOUT = 1.8 V IOUT = 0 A 75 100
Power supply voltage VIN (V)
Ambient temperature Ta ( C)
Oscillation frequency - VREFIN voltage
1.2 0.7
SW FET ON resistance vs. Power supply voltage SW FET ON resistance R (ON) ()
Oscillation frequency fosc (MHz)
1.0
0.6 0.5 0.4 0.3 0.2 0.1 Ta = +25 C 0.0 2 3 4 5 6 Nch Pch
0.8
0.6
0.4 Ta = +25 C VIN = 3.7 V IOUT = 200 mA 0.0 0.2 0.4 0.6 0.8 1.0
0.2
0.0
VREFIN voltage (V)
Power supply voltage VIN (V)
(Continued)
13
MB39C001
Pch SW FET ON resistance vs. Ambient temperature Pch SW FET ON resistance RP (ON) ()
VIN = 2.5 V 0.6 VIN = 3.7 V 0.5 0.4 0.3 0.2 0.1 0.0 -50
Nch SW FET ON resistance vs. Ambient temperature Nch SW FET ON resistance RN (ON) ()
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -50 VIN = 5.5 V VIN = 2.5 V VIN = 3.7 V
0.7
VIN = 5.5 V
-25
0
25
50
75
100
-25
0
25
50
75
100
Ambient temperature Ta ( C)
Ambient temperature Ta ( C)
Power dissipation vs. Ambient temperature
600
Power dissipation PD (mW)
540
500 400 300 200 100 0 -50 -25
85 210
0
25
50
75
100 125
Ambient temperature Ta ( C)
(Continued)
14
MB39C001
Output waveforms at load sudden changes
VOUT 200 mV/div
IOUT 0.5 A/div
20 s/div
VIN = 3.7 V VOUT = 1.8 V IOUT = 0 mA to 600 mA
Output waveforms at load sudden changes
VOUT 200 mV/div
IOUT 0.5 A/div
20 s/div
VIN = 3.7 V VOUT = 1.8 V IOUT = 200 mA to 600 mA
(Continued)
15
MB39C001
Output waveforms at load sudden changes
VOUT 200 mV/div
IOUT 0.5 A/div
20 s/div
VIN = 3.7 V VOUT = 1.8 V IOUT = 100 mA to 600 mA
Switching waveforms (continuous operation)
VOUT 20 mV/div
VLX 2 V/div
ILX 0.5 A/div
400 ns/div
VIN = 3.7 V VOUT = 1.8 V IOUT = 600 mA
(Continued)
16
MB39C001
(Continued)
Switching waveforms (during burst operation)
VOUT 100 mV/div
VLX 2 V/div
ILX 0.5 A/div
2 s/div
VIN = 3.7 V VOUT = 1.8 V IOUT = 100 mA
CNT terminal response characteristics
VOUT 1 V/div
ILX 0.5 A/div
VCNT 2 V/div
20 s/div
VIN = 3.7 V VOUT = 1.8 V IOUT = 600 mA
17
MB39C001
s TYPICAL OPERATING CHARACTERISTICS MEASUREMENT CIRCUIT
VDD
VDD AVDD OUT C5 x3 VRSEL VSET1 to VSET3 CNT AGND DVDD1, DVDD2
VDD VIN C2 LX1, LX2 L1 C1 GND DGND1, DGND2 VOUT
Load current
lOUT
R1
COMPONENT R1 C2 C5 C1 L1 Resistor
ITEM Ceramic condenser Ceramic condenser Ceramic condenser Inductor
Specification 1 M 4.7 F 0.01 F 10 F 3.3 H
Vendor ssm TDK TDK TDK TDK
Parts No. PFR05Q-105-D-1 C2012JB1A475K C1608JB1H103K C2012JB0J106M VLF4012AT-3R3M
ssm : SUSUMU CO., LTD. TDK : TDK Corporation
Note : The above components are recommended parts confirmed by Fujitsu to operate normally.
18
MB39C001
s APPLICATION NOTES
(1) Selection of components
* Selection of external inductor
The design of the inductor is basically unnecessary. This IC is designed to operate efficiently with a 3.3 H inductor. Select the inductor whose rated saturation current is larger than the LX peak current in the operating conditions, and select the inductor whose DC resistance is as low as possible (150 m or less is recommended) . The LX peak current value (IPK) is obtained from the following formula : IPK = IOUT + VIN - VOUT L * D * fsw 1 2 = IOUT + (VIN - VOUT) * VOUT 2 * L * fsw * VIN
L VIN D
: External inductor value : Power supply voltage : Switching on-duty cycle ( = VOUT / VIN)
IOUT : Load current VOUT : Output setting voltage fosc : Switching frequency (fixed at 1 MHz) Example : Peak current maximum value (IPK) : At VIN = 3.7 V, VOUT = 1.8 V, IOUT = 0.6 A, L = 3.3 H. IPK = IOUT + (VIN - VOUT) * VOUT (3.7 V - 1.8 V) * 1.8 V = 0.6 A + = 0.74 A : 2 * 3.3 H * 1 MHz * 3.7 V 2 * L * fsw * VIN
* Selection of I/O condenser
* Select the DVDD input condenser whose equivalent series resistance (ESR) is low in particular, to suppress the loss by ripple currents. * Better line regulation and load regulation characteristics can be obtained by adding an input condenser immediately close to AVDD. Although the appropriate capacitance may be different depending on the layout design, the reference range for selection is from , 1000 pF to 0.01 F. * The output condenser should also have low equivalent series resistance (ESR). The ripple current of the fluctuation portion of the inductor current, it flows into the output condenser. The ripple voltage is the product of this fluctuation portion and ESR, it is generated at the output. The output capacitance significantly affects the stability of operation as a DC/DC converter. In principle, an output condenser of about 10 F is recommended. If there is a problem with the ripple voltage, you can work around the problem by selecting one with large capacitance. * Condenser types Selecting ceramic condenser for both of input and output is effective for reduction in ESR and size. Since power supply circuits are heat generators, you should avoid using ceramic condenser which have an F temperature characteristic (-80% to +20%). You should use those with a B characteristic ( 10% to 20%) or the like. Avoid using normal electrolytic condenser as their ESR is high. Tantalum condenser are effective for reduction in ESR but are very dangerous as they have a disadvantage, they establish a short mode if a failure occurs. When using a Tantalum condenser, choose one with a fuse.
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MB39C001
(2) Setting output voltages When output voltages are set in advance, only treat the control terminals as shown in the table below. Any additional component such as a voltage dividing resistor is not required. As VSET1 to VSET3, VSEL, and VRSEL terminals have built-in pull-down equal circuits, their level is equal to "L" when opened. Note : For a circuit configuration example, refer (1) "Setting 1.8-V output using the internal reference voltage" in s APPLICATION EXAMPLES. * Output voltage setting table 1 VSET1 VSET2 L H H L H H L L H L H X : Don't care To set arbitrary voltages other than above, set VRSEL to "H" and apply voltage to VREFIN. The voltage applied to VREFIN is supplied either from external or by dividing VREF using a resistor. The output voltage using VREFIN with VREF resistor-divided is obtained from the following formula : VOUT = (Output voltage setting value) * Kv R8 R7 + R8 Kv = R8 * R7 + R8 1.25 0.6 L L L H H H L L L H H VSET3 L L L L L L H H H H H VSEL X L H X L H L H X X X L VRSEL VOUT 1.1 V 0.8 V 1.2 V 1.3 V 1.1 V 1.5 V 1.1 V 1.8 V 2.5 V 2.8 V 3.3 V
(VREFIN voltage :
x 1.25 Refer (4) "VREFIN terminal in s NOTES ON CIRCUIT DESIGN".
Note : For a circuit configuration example, refer (2) "Supplying the VREF terminal voltage to the reference voltage external input (VREFIN) after resistor voltage division and setting the VOUT voltage to 1.25 V with VOUT setting gain doubled" in s APPLICATION EXAMPLES. The output voltage is determined by the resistor ratio. Select the resistance value so that the current flowing through the resistor does not exceed the rated VREF current (1 mA) .
20
MB39C001
* Output voltage setting table 2 VSET1 VSET2 VSET3 L H H L H H L L H L H X : Don't care (3) About conversion efficiency The conversion efficiency can be improved by reducing the loss of the DC/DC converter circuit. The total loss (PLOSS) of the DC/DC converter is roughly divided as follows : PLOSS = PCONT + PSW + PC PCONT : Control system circuit loss (The power used for this IC to operate, including the the gate driving power for internal SW FETs) PSW PC : Switching loss (The loss caused during switching of the IC's internal SW FETs) : Continuity loss (The loss caused when currents flow through the IC's internal SW FETs and external circuits ) L L L H H H L L L H H L L L L L L H H H H H
VSEL X L H X L H L H X X X
VRSEL
VOUT (Output voltage setting value x Kv) 1.1 V x Kv 0.8 V x Kv 1.2 V x Kv 1.3 V x Kv 1.1 V x Kv
H
1.5 V x Kv 1.1 V x Kv 1.8 V x Kv 2.5 V x Kv 2.8 V x Kv 3.3 V x Kv
The IC's control circuit loss (PCONT) is extremely small, which is about 1 mW (IIN = 300 A) * , at VIN = 3.7 V. As the IC contains FETs which can switch faster with smaller power, the continuity loss (PC) is more predominant as the loss during heavy-load operation than the control circuit loss (PCONT) and switching loss (PSW) . Further the continuity loss (PC) is divided roughly, into the loss by internal SW FET ON-resistance and by external inductor series resistance. PC = IOUT2 * (RDC + D * RONp + (1 - D) * RONn) D : Switching on-duty cycle ( = VOUT / VIN)
RONp : Internal Pch SW FET ON resistance RONn : Internal Nch SW FET ON resistance RDC : External inductor series resistance IOUT = Load current
21
MB39C001
The above formula indicates that it is important to reduce RDC as much as possible to improve efficiency by selecting components. * : The loss is caused during continuous operation. When the load is light, the IC performs burst operation, thereby further suppressing the loss (IIN = about 30 A with no load). The mode is changed depending on the peak current value Ipk flowing into SW FETs, at a threshold value of about 150 mA. (4) Power dissipation and temperature examination The IC is so efficient that no examination is required in most cases. But if the IC is used at a low power supply voltage, heavy load, high output voltage, or high temperature, it requires further examination for higher efficiency. The internal loss (P) is roughly obtained from the following formula : P = IOUT2 * (D * RONp + (1 - D) * RONn) D : Switching on-duty cycle ( = VOUT / VIN)
RONp : Internal Pch SW FET ON resistance RONn : Internal Nch SW FET ON resistance IOUT = Load current The loss expressed by the above formula is mainly continuity loss. The internal loss includes the switching loss and the control circuit loss as well but they are so small compared to the continuity loss they can be ignored. In this IC with RONp greater than RONn, the larger the on-duty cycle, the greater the loss. When assuming VIN = 3.7 V, Ta = 70 C, VOUT = 1.8 V, and IOUT = 0.6 A, for example, RONp = 0.48 and RONn = 0.39 according to the graph "SW FET ON resistance vs. Ambient temperature". The IC's internal loss P is 156 mW. According to the graph "Power dissipation vs. ambient temperature", the power dissipation at an ambient temperature Ta of 70 C is 300 mW and the internal loss is smaller than the power dissipation. (5) Transient response The IC contains an optimized version of ErrAmp, providing favorable transient response characteristics. The response characteristics such as response time, overshoot, and undershoot, are checked usually by changing suddenly IOUT, with VIN and VOUT left constant. (6) Example of designing board layout For stable operation, the IC requires the optimized design of board layout. Pay attention to the following points during layout design. * Connect the GND terminals (AGND, DGND1, DGND2) and power terminals (AVDD, DVDD1, DVDD2) immediately near the IC. * Place the DVDD input condenser (C2) near DVDD and DGND. If the power supply or ground plains exists on any other board layer, place TH (through hole) close to the condenser terminal. * Place the AVDD input condenser (C5) near AVDD and AGND. If the power supply or ground plains exists on any other board layer, place TH (through hole) close to the condenser terminal.
22
MB39C001
* Place the GND side terminal of the output condenser (C1) as near DGND of the IC and the GND side terminal of the input condenser (C2). If the ground plains exists on any other board layer, place TH close to the GND side terminal of the condenser. For wiring to OUT, start close to the VOUT side terminal of the output condenser (CI). Note that the OUT terminal is highly sensitive and should be wired as apart from the wiring of the LX terminal of the IC. * Large currents flow among the input condenser (C2, C5), output condenser (C1), external inductor (L1), and this IC. Place these components near the IC, to minimize the loop area made up of these components. Also, mount these components on the same layer and wire them without using any TH. Wire these nets using as bold, short, and straight patterns (plains layout is advisable). * For the IC mounted layer, provide a ground plane.
Recommended layout drawing (with only important wiring)
VIN C2
TH
C5 MB39C001 L1
GND C1
VOUT
23
MB39C001
s NOTES ON CIRCUIT DESIGN
(1) GND Potential Connect AGND and DGND to GND of the power supply circuit, so that they have equal potential. (2) Control input terminals * The voltages applied to the CNT, VSET1 to VSET3, VSEL, and VRSEL terminals must not exceed the absolute maximum rating (VDD + 0.3 V). Applying a voltage exceeding the absolute maximum rating may cause permanent damage to the LSI. If it is inevitable, insert a resistor of about 20 k between a terminal of the controller (such as a CPU) and the control terminal of the IC. This prevents a latch-up to some extent. Note : Finally, judge right or wrong of the adoption after confirming it is unquestionable under your system requirements as permanent measure. * The CNT terminal has no internal pull-down resistor function (while the VSET1 to VSET3, VSEL, and VRSEL have one). If the terminal of the controller (such as the CPU) connected to the CNT terminal can enter a high impedance state an unpredictable malfunction may occur. To prevent this, a pull-down resistor (of about 1 M) should be connected to the CNT terminal. * If the fall time of the CNT terminal is long, the output (VOUT) may cause an overshoot when the load is light. Be careful not to let the rise time and fall time exceed 500 s. (3) Power supply input * If the rise time or fall time of the supply voltage (VIN) is long, a malfunction may occurs. Be careful not to let the rise time and fall time exceed 100 ms. * If the power supply voltage fluctuates around the UVLO detection voltage (between 2.15 and 2.3 V) when the power supply is turned on or shut off. The output is stopped by under-voltage and restarted by restored voltage repeatedly and there is a possibility that chattering is generated in VOUT. Although the UVLO detection voltage has a hysteresis of 0.15 V, fluctuation over 0.15 V cannot be suppressed. Be careful to prevent the supply voltage from going up and down near UVLO. * If the CNT terminal becomes "L" from "H" when the supply voltage (VIN) becomes lower than the output voltage (VOUT), the IC may cause a latch-up by the action of an external inductor. Although this is an operating condition unintended for normal use, it can occur frequently when the power supply voltage is shut off with light loads. Even if a latch-up occurs by normal shutdown, the latch-up is cleared when the power supply voltage goes below 0.8 V. Therefore, there are few things which become problem, when the power supply is turned back on again. If the power supply is turned back on with the power supply voltage exceeding 0.8 V, the IC may be broken by an excessive current due to a latch-up. This problem can be worked around by either of the following two methods : * When the CNT terminal becomes "L" from "H" as the power supply voltage goes down, be sure to lower the power supply voltage to 0.8 V or less before turning the power supply back on again. * Add a Schottky barrier diode as shown in the latch-up preventive circuit example. Note, however, that this work around adversely affects the regulation or conversion efficiency when the application uses an extremely small load current. When selecting the Schottky barrier diode, pay attention to the following points : Reverse current [IR] Select a diode whose reverse current is smaller than the load current. (If a diode whose reverse current is greater than the load current is adopted, the output voltage (VOUT) is raised by the reverse current, and the regulation deteriorates. 24
MB39C001
Forward voltage [VF] The forward voltage must be smaller than the voltage triggering latch-up. Select a diode whose forward voltage is about 0.5 V or less. Non repetitive peak surge current [IFSM] Select a diode whose non repetitive peak surge current is greater than the peak reverse current. The peak current is different depending on the operating conditions; the reference value is 1 A to 3 A. Latch-up preventive circuit example Schottky barrier diode for latch-up prevention
VIN 10 14 15 AVDD DVDD1 DVDD2 LX1 1 LX2 2 OUT 4 AGND DGND1 DGND2 8 17 18 VOUT
(4) VREFIN terminal When the VREFIN terminal is used, the switching frequency is lowered if the VREFIN voltage is 0.5 V or less. When the load current (IOUT) is 100 mA or less, the VREFIN voltage should fall within the range of 0.5 to 0.7 V. The VREFIN voltage can be between 0.3 and 0.7 V if the switching frequency lowered is acceptable when the load current (IOUT) is 100 mA or less. (5) POWER GOOD terminal The POWER GOOD terminal always monitors the OUT terminal voltage, with no exception, even when the output voltage is changed by switching the terminals such as VSET1 to VSET3 and VSEL. When the output voltage rises slowly with heavy loads, the POWER GOOD terminal become "H" until the output voltage becomes 90% of the setting voltage. Be careful when using the POWER GOOD terminal to reset a load circuit which uses a CPU. Be careful that the POWER GOOD terminal temporarily becomes "H" level when dynamically changing the voltage, thereby resetting the circuit accidentally at an unintended timing. (6) Output overcurrent protection This IC uses current mode control which provides a certain level of overcurrent protection. If LX is connected to VDD or GND, or VOUT is connected to GND with an extremely low resistor of 0.1 or less, the IC may not be protected from overcurrents and it is break down. The IC is apt to break down, when the inductance element of the short-circuit route is large or when the output voltage is high. To prevent the IC from breaking due to a short-circuit, it is advisable to insert a resistor of about 1 k between the OUT terminal and VOUT. 25
MB39C001
s APPLICATION EXAMPLES
(1) Output setting of 1.8 V by reference voltage use of internal
C5 0.01 F
10 AVDD VSET1 VSET2 VSET3 VSEL
CPU
R2 20 k R1 1 M
13 12 11 16
14 15 DVDD1 DVDD2 LX1 LX2 OUT POWER GOOD
C2 4.7 F 1 2 4 6 L1 3.3 H
VIN VOUT C1 10 F R6 1 M
9 CNT
APLI
3 VRSEL 5 VREF 7 VREFIN AGND DGND1 DGND2 8 17 18
(2) Supplying the VREF terminal voltage to the reference voltage external input (VREFIN) after resistor voltage division, the VOUT voltage is set to 1.25 V by the OUT setting gain twice
C5 0.01 F
10 AVDD VSET1 VSET2 VSET3 VSEL
CPU
R2 20 k R1 1 M
13 12 11 16
14 15 DVDD1 DVDD2 LX1 LX2 OUT POWER GOOD
C2 4.7 F 1 2 4 6 L1 3.3 H
VIN VOUT C1 10 F
9 CNT
APLI
3 VRSEL 5 VREF 7 VREFIN AGND DGND1 DGND2 8 17 18
R7 100 k R8 100 k
VOUT = (Output voltage setting value ) x =
VREFIN 0.6
1.2 R8 * VREFIN = 2 x VREF 0.6 R7 + R8 100 k x 1.25 = 1.25 V 100 k + 100 k
=2x
26
MB39C001
(3) Supplying an external voltage to the reference voltage external input (VREFIN), the VOUT voltage is set by the VOUT setting gain triple
C5 0.01 F
10 AVDD VSET1 VSET2 VSET3 VSEL
CPU
R2 20 k R1 1 M
13 12 11 16
14 15 DVDD1 DVDD2 LX1 LX2 OUT POWER GOOD
C2 4.7 F 1 2 4 6 L1 3.3 H
VIN VOUT C1 10 F
9 CNT
APLI
3 VRSEL 5 VREF DAC 7 VREFIN AGND DGND1 DGND2 8 17 18
VOUT = (Output voltage setting value ) x = 1.8 * VREFIN = 3 x VREFIN 0.6
VREFIN 0.6
The components for the above example are listed below. Component Part name Specification L1 C1 C2 C5 R1 R2 R6 R7 R8 TDK ssm Inductor Ceramic condenser Ceramic condenser Ceramic condenser Resistor Resistor Resistor Resistor Resistor 3.3 H 10 F 4.7 F 0.0 1 F 1 M 20 k 1 M 100 k 100 k 20% RDC = 120 m 20% 6.3 V 10% 10 V 10% 50 V 0.5% 0.5% 0.5% 0.5% 0.5%
Manufacturer
Model name VLF4012AT-3R3M C2012JB0J106M C2012JB1A475K C1608JB1H103K PFR05Q-105-D-1 RR0816P-203-D PFR05Q-105-D-1 RR0816P-104-D RR0816P-104-D
TDK TDK TDK TDK ssm ssm ssm ssm ssm
: TDK Corporation : SUSUMU CO., LTD.
27
MB39C001
s NOTES ON USE
1. Do not exceed maximum ratings.
Using the LSI beyond maximum ratings may generate a parasitic transistor, resulting in permanent damage to the LSI due to a latch-up. The LSI should be used under the recommended operating conditions and exceeding any of the recommended conditions may adversely affect LSI reliability.
2. Use under recommended operating conditions.
The recommended operating conditions are reommended values that guarantee the normal operation of the LSI. The values of electrical characteristics are guaranteed when the LSI is used under the recommended operating conditions with each parameter falling in the specified range.
3. Take measures against static electricity.
* Containers for semiconductors must be antistatic or conductive. * When storing or carrying a printed circuit board with components mounted, put it in a conductive bag or container. * The work table, tools, and measuring instruments must be properly grounded. * The worker must put on a grounding device containing 250 k to 1 M resistors in series.
4. Do not apply a negative voltage.
Applying a negative voltage of - 0.3 V or less to an LSI may generate a parasitic transistor, resulting malfunction.
s ORDERING INFORMATION
Model MB39C001PVB Package 18-pin plastic BCC (LCC-18P-M05) Remarks
28
MB39C001
s PACKAGE DIMENSIONS
18-pin plastic BCC (LCC-18P-M05)
2.700.10 (.106.004) 0.450.05 (.018.002) (Mount height) 2.31(.090) TYP 0.45(.018) TYP.
15
10
10
15
INDEX AREA
2.400.10 (.094.004)
2.01(.079) TYP 0.45(.018) TYP. 0.0750.025 (.003.001) (Stand off) "A" "C" "B"
0.90(.035) REF 1.90(.075) REF
1
6
6
1.35(.053) REF 2.28(.090) REF
1
Details of "A" part 0.05(.002) 0.14(.006) MIN. 0.250.06 (.010.002)
Details of "B" part C0.10(.004) 0.360.06 (.014.002)
Details of "C" part 0.360.06 (.014.002)
0.250.06 (.010.002)
0.280.06 (.011.002)
0.280.06 (.011.002)
C
2003 FUJITSU LIMITED C18058S-c-1-1
Unit : mm (inches) Note : Parenthesized values are reference values.
29
MB39C001
s EVALUATION BOARD SPECIFICATIONS
The MB39C001 evaluation board is a surface-mounting board of a single-channel down-conversion circuit. The output voltage can be set by switch of each SW (*1), and supplies the current of up to 600 mA at a power supply voltage from 2.5 V to 5.5 V (*2). *1 : For setting the output voltage, refer (2) "Setting output voltages" in s APPLICATION NOTES. *2 : The current can be supplied when "VIN - VOUT 0.7 V". It can be supplied even "VIN - VOUT < 0.7 V" when under operating conditions in which the output current is suppressed.
* Terminal Description
Symbol VIN OUT VCTL Power supply terminal. VIN = 2.5 V to 5.5 V (3.7 V Typ) DC/DC converter output terminal.
Function
Power supply terminal for mode setting SW. Connect with VIN and use it. Power control terminal. VCNT = 0 V to 0.3 V : Shutdown VCNT = 1.5 V to VIN : Normal operation Fixed at "L" ( = 0 V) , when the OUT voltage reaches the output setting voltage. Reference voltage output terminal. External reference voltage input terminal. When an external reference voltage is used, this terminal supplies it. DC/DC converter ground terminal. MB39C001 ground terminal.
CNT POWER_GOOD VREF VREFIN GND AGND
* Switch Description
SW 1 2 3 4 5
Name VSEL VSET1 VSET2 VSET3 VRSEL
FUNCTION Output voltage setting Output voltage setting Output voltage setting Output voltage setting Reference voltage setting
Remarks
For details on each setting, refer (2) "Setting output voltages" in s APPLICATION NOTES.
* Setup and checkup
(1) Setup Connect the power supply terminal of the power supply to VIN, VCTL, and CNT and its ground terminal to GND. Connect the OUT side to the required loading device or measuring instrument. Set SW1 (VSEL) and SW4 (VSET3) to ON; SW2 (VSET1), SW3 (VSET2), and SW5 (VRSEL) to OFF. (Set the output to 1.8 V using the internal reference voltage.) (2) Checkup Supply power to VIN. The IC is working normally when the OUT voltage is 1.8 V (Typ) . 30
MB39C001
* On-board Component Layout
Top side (Top View)
1 2 3 4 5 6 AGND CNT VSEL VSET1 VSET2 VSET3 VRSEL N. C
SW1 VCTL
VIN
VREFIN
C2 GND C1
M1
C5 R8 R6 R7 C3 L1 VREF POWER_GOOD
OUT
Bottom side (Top View)
4C
31
MB39C001
Board Layout
Top Side (Layer1)
In Side VIN & GND (Layer2)
Inside GND (Layer3)
Bottom Side (Layer4)
32
MB39C001
* Connection Diagram
IIN VIN C2 4.7 F VCTL SW2 SW3 SW4 SW1 CNT SW5 3 VREF VREFIN R8 100 k C3 0.1 F R7 100 k 5 7 8 17 18 AGND GND MB39C001 C5 0.01 F 10 13 12 11 16 9 6 14 15 1 2 4 L1 3.3 H C1 10 F R6 1 M POWER GOOD C4 IOUT OUT
* Parts List
Symbol L1 C1 C2 C3 C4 C5 R6 R7 R8 SW
Part name Inductor Ceramic capacitor Ceramic capacitor Ceramic capacitor Ceramic capacitor Resistor Resistor Resistor Switch Terminal pins : : : :
Model name VLF4012AT-3R3M C2012JB0J106M C2012JB1A475K C1608JB1H104K C1608JB1H103K PFR05Q-105-D-1 RR0816P-104-D RR0816P-104-D DMS-6H WT-2-1
Specification 3.3 H, RDC = 120 m 10 F (6.3 V) 4.7 F (10 V) 0.1 F (50 V) 0.01 F (50 V) 1 M 0.5% 100 k 0.5% 100 k 0.5% 6 poles WT-2-1
Package SMD 2012 2012 1608 1608 1005 1608 1608
Manufacturer
Remarks
TDK TDK TDK TDK TDK ssm ssm ssm MATSUKYU MacEight
Not mounted
TDK ssm MATSUKYU MacEight
TDK Corporation SUSUMU CO., LTD. Matsukyu Co., Ltd. MacEight Co., Ltd.
* Ordering Information
EV board part No. MB39C001EVB-01
EV board version No. MB39C001EV Board Rev.2.0
Remarks
33
MB39C001
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0405 (c) FUJITSU LIMITED Printed in Japan

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